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authorMarcelo Tosatti <mtosatti@redhat.com>2011-10-24 21:27:16 -0200
committerMarcelo Tosatti <mtosatti@redhat.com>2011-10-24 21:27:16 -0200
commit38d2c27ea68468bd2fdaa19c74d9e6d290f94777 (patch)
treecbcd13b723a13aaac47773e4628e1c56e508a56d /target-i386
parent1cae88b9f4121c9af0bf677435c6129e643280fd (diff)
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Revert "kvm: support TSC deadline MSR"
This reverts commit bfc2455ddbb41148494a084d15777e6bed7533c3. New patch with subsections will follow. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'target-i386')
-rw-r--r--target-i386/cpu.h4
-rw-r--r--target-i386/kvm.c14
-rw-r--r--target-i386/machine.c1
3 files changed, 1 insertions, 18 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index a973f2e..ae36489 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -283,7 +283,6 @@
#define MSR_IA32_APICBASE_BSP (1<<8)
#define MSR_IA32_APICBASE_ENABLE (1<<11)
#define MSR_IA32_APICBASE_BASE (0xfffff<<12)
-#define MSR_IA32_TSCDEADLINE 0x6e0
#define MSR_MTRRcap 0xfe
#define MSR_MTRRcap_VCNT 8
@@ -688,7 +687,6 @@ typedef struct CPUX86State {
uint64_t async_pf_en_msr;
uint64_t tsc;
- uint64_t tsc_deadline;
uint64_t mcg_status;
@@ -949,7 +947,7 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_list_id x86_cpu_list
#define cpudef_setup x86_cpudef_setup
-#define CPU_SAVE_VERSION 13
+#define CPU_SAVE_VERSION 12
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 90a6ffb..b6eef04 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -59,7 +59,6 @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
static bool has_msr_star;
static bool has_msr_hsave_pa;
-static bool has_msr_tsc_deadline;
static bool has_msr_async_pf_en;
static int lm_capable_kernel;
@@ -569,10 +568,6 @@ static int kvm_get_supported_msrs(KVMState *s)
has_msr_hsave_pa = true;
continue;
}
- if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {
- has_msr_tsc_deadline = true;
- continue;
- }
}
}
@@ -886,9 +881,6 @@ static int kvm_put_msrs(CPUState *env, int level)
if (has_msr_hsave_pa) {
kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
}
- if (has_msr_tsc_deadline) {
- kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline);
- }
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
@@ -1135,9 +1127,6 @@ static int kvm_get_msrs(CPUState *env)
if (has_msr_hsave_pa) {
msrs[n++].index = MSR_VM_HSAVE_PA;
}
- if (has_msr_tsc_deadline) {
- msrs[n++].index = MSR_IA32_TSCDEADLINE;
- }
if (!env->tsc_valid) {
msrs[n++].index = MSR_IA32_TSC;
@@ -1206,9 +1195,6 @@ static int kvm_get_msrs(CPUState *env)
case MSR_IA32_TSC:
env->tsc = msrs[i].data;
break;
- case MSR_IA32_TSCDEADLINE:
- env->tsc_deadline = msrs[i].data;
- break;
case MSR_VM_HSAVE_PA:
env->vm_hsave = msrs[i].data;
break;
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 25fa97d..9aca8e0 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -410,7 +410,6 @@ static const VMStateDescription vmstate_cpu = {
VMSTATE_UINT64_V(xcr0, CPUState, 12),
VMSTATE_UINT64_V(xstate_bv, CPUState, 12),
VMSTATE_YMMH_REGS_VARS(ymmh_regs, CPUState, CPU_NB_REGS, 12),
- VMSTATE_UINT64_V(tsc_deadline, CPUState, 13),
VMSTATE_END_OF_LIST()
/* The above list is not sorted /wrt version numbers, watch out! */
},