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| author | Liu, Jinsong <jinsong.liu@intel.com> | 2011-09-25 16:10:48 +0800 |
|---|---|---|
| committer | Marcelo Tosatti <mtosatti@redhat.com> | 2011-10-03 13:53:14 -0300 |
| commit | bfc2455ddbb41148494a084d15777e6bed7533c3 (patch) | |
| tree | 4f60ef4b70896fa8353c11e715c96bad6c403aa1 /target-i386/cpu.h | |
| parent | d11cf8cc80d946dfc9a23597cd9a0bb1c487cfa7 (diff) | |
| download | qemu-bfc2455ddbb41148494a084d15777e6bed7533c3.zip qemu-bfc2455ddbb41148494a084d15777e6bed7533c3.tar.gz qemu-bfc2455ddbb41148494a084d15777e6bed7533c3.tar.bz2 | |
kvm: support TSC deadline MSR
KVM add emulation of lapic tsc deadline timer for guest.
This patch is co-operation work at qemu side.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index ae36489..a973f2e 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -283,6 +283,7 @@ #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x6e0 #define MSR_MTRRcap 0xfe #define MSR_MTRRcap_VCNT 8 @@ -687,6 +688,7 @@ typedef struct CPUX86State { uint64_t async_pf_en_msr; uint64_t tsc; + uint64_t tsc_deadline; uint64_t mcg_status; @@ -947,7 +949,7 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define cpu_list_id x86_cpu_list #define cpudef_setup x86_cpudef_setup -#define CPU_SAVE_VERSION 12 +#define CPU_SAVE_VERSION 13 /* MMU modes definitions */ #define MMU_MODE0_SUFFIX _kernel |