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| author | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-01-04 17:20:53 +0000 |
|---|---|---|
| committer | bellard <bellard@c046a42c-6fe2-441c-8c8c-71466251a162> | 2004-01-04 17:20:53 +0000 |
| commit | 65262d57382c228ed62b90a94a0968eb0167bb2d (patch) | |
| tree | c097bc39805a549059323c28aa3d011d94756d65 /target-i386/cpu.h | |
| parent | 773b93ee0684a9b9d1f0029a936a251411289027 (diff) | |
| download | qemu-65262d57382c228ed62b90a94a0968eb0167bb2d.zip qemu-65262d57382c228ed62b90a94a0968eb0167bb2d.tar.gz qemu-65262d57382c228ed62b90a94a0968eb0167bb2d.tar.bz2 | |
added PE to static CPU state (avoids flushing translated code when swiching between protected and real mode) - moved memory defs to cpu-all.h
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@504 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-i386/cpu.h')
| -rw-r--r-- | target-i386/cpu.h | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 07e48c0..6be987c 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -106,6 +106,11 @@ #define HF_SS32_SHIFT 5 /* zero base for DS, ES and SS */ #define HF_ADDSEG_SHIFT 6 +/* copy of CR0.PE (protected mode) */ +#define HF_PE_SHIFT 7 +#define HF_TF_SHIFT 8 /* must be same as eflags */ +#define HF_IOPL_SHIFT 12 /* must be same as eflags */ +#define HF_VM_SHIFT 17 /* must be same as eflags */ #define HF_CPL_MASK (3 << HF_CPL_SHIFT) #define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT) @@ -113,6 +118,7 @@ #define HF_CS32_MASK (1 << HF_CS32_SHIFT) #define HF_SS32_MASK (1 << HF_SS32_SHIFT) #define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT) +#define HF_PE_MASK (1 << HF_PE_SHIFT) #define CR0_PE_MASK (1 << 0) #define CR0_TS_MASK (1 << 3) @@ -391,9 +397,6 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info, /* MMU defines */ void cpu_x86_init_mmu(CPUX86State *env); -extern int phys_ram_size; -extern int phys_ram_fd; -extern uint8_t *phys_ram_base; extern int a20_enabled; void cpu_x86_set_a20(CPUX86State *env, int a20_state); |