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| author | Ian Campbell <ijc@hellion.org.uk> | 2014-06-09 15:43:23 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-06-09 16:06:11 +0100 |
| commit | d615efac7c4dc0984de31791c5c7d6b06408aadb (patch) | |
| tree | 67c5dea7fb5be28d91bb92c80428ba354ba67051 /target-arm | |
| parent | 8d5c773e323b22402abdd0beef4c7d2fc91dd0eb (diff) | |
| download | qemu-d615efac7c4dc0984de31791c5c7d6b06408aadb.zip qemu-d615efac7c4dc0984de31791c5c7d6b06408aadb.tar.gz qemu-d615efac7c4dc0984de31791c5c7d6b06408aadb.tar.bz2 | |
target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes
and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we
can just treat this bit as UXN whenever we are in v8 mode.
Also correctly extract the upper attributes from the PTE entry, the v8 version
tried to avoid extracting the CONTIG bit and ended up with the upper bits being
off-by-one. Instead behave the same as v7 and extract (but ignore) the CONTIG
bit.
This fixes "Bad mode in Synchronous Abort handler detected, code 0x8400000f"
seen when modprobing modules under Linux.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Claudio Fontana <claudio.fontana@huawei.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
| -rw-r--r-- | target-arm/helper.c | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 3e7f0db..1e50a78 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3929,13 +3929,8 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, page_size = (1 << ((granule_sz * (4 - level)) + 3)); descaddr |= (address & (page_size - 1)); /* Extract attributes from the descriptor and merge with table attrs */ - if (arm_feature(env, ARM_FEATURE_V8)) { - attrs = extract64(descriptor, 2, 10) - | (extract64(descriptor, 53, 11) << 10); - } else { - attrs = extract64(descriptor, 2, 10) - | (extract64(descriptor, 52, 12) << 10); - } + attrs = extract64(descriptor, 2, 10) + | (extract64(descriptor, 52, 12) << 10); attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */ attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */ /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1 @@ -3961,8 +3956,12 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address, goto do_fault; } *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) { - /* XN or PXN */ + if ((arm_feature(env, ARM_FEATURE_V8) && is_user && (attrs & (1 << 12))) || + (!arm_feature(env, ARM_FEATURE_V8) && (attrs & (1 << 12))) || + (!is_user && (attrs & (1 << 11)))) { + /* XN/UXN or PXN. Since we only implement EL0/EL1 we unconditionally + * treat XN/UXN as UXN for v8. + */ if (access_type == 2) { goto do_fault; } |