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author | Nathan Rossi <nathan.rossi@xilinx.com> | 2013-10-25 15:44:38 +0100 |
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committer | Edgar E. Iglesias <edgar.iglesias@gmail.com> | 2013-10-31 14:00:16 +0100 |
commit | 8641136c54d216edb5bb8ef723c754039b4c5cf3 (patch) | |
tree | c0497b6034670052d2e64ad2226a32e07b01a340 /target-arm | |
parent | dacecf5485bf02b2dfe49e9d9c852668884a71be (diff) | |
download | qemu-8641136c54d216edb5bb8ef723c754039b4c5cf3.zip qemu-8641136c54d216edb5bb8ef723c754039b4c5cf3.tar.gz qemu-8641136c54d216edb5bb8ef723c754039b4c5cf3.tar.bz2 |
target-arm: Add CP15 VBAR support
Added Vector Base Address remapping on ARM v7.
Signed-off-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
[PMM: removed spurious mask of value with 1<<31]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm')
-rw-r--r-- | target-arm/cpu.h | 1 | ||||
-rw-r--r-- | target-arm/helper.c | 21 |
2 files changed, 22 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2c56740..9f110f1 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -176,6 +176,7 @@ typedef struct CPUARMState { uint32_t c9_pmxevtyper; /* perf monitor event type */ uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ + uint32_t c12_vbar; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint32_t c13_context; /* Context ID. */ uint32_t c13_tls1; /* User RW Thread register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index c63bbd7..73476ed 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -537,6 +537,13 @@ static int pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, return 0; } +static int vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + env->cp15.c12_vbar = value & ~0x1Ful; + return 0; +} + static int ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t *value) { @@ -622,6 +629,10 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten), .resetvalue = 0, .writefn = pmintenclr_write, }, + { .name = "VBAR", .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, + .access = PL1_RW, .writefn = vbar_write, + .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), + .resetvalue = 0 }, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), .resetvalue = 0, }, @@ -2470,7 +2481,17 @@ void arm_cpu_do_interrupt(CPUState *cs) } /* High vectors. */ if (env->cp15.c1_sys & (1 << 13)) { + /* when enabled, base address cannot be remapped. */ addr += 0xffff0000; + } else { + /* ARM v7 architectures provide a vector base address register to remap + * the interrupt vector table. + * This register is only followed in non-monitor mode, and has a secure + * and un-secure copy. Since the cpu is always in a un-secure operation + * and is never in monitor mode this feature is always active. + * Note: only bits 31:5 are valid. + */ + addr += env->cp15.c12_vbar; } switch_mode (env, new_mode); env->spsr = cpsr_read(env); |