diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-23 15:36:43 +0000 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-26 15:09:41 +0000 |
commit | 50866ba5a2cfe922aaf3edb79f6eac5b0653477a (patch) | |
tree | 39acd126ce238393135ebce39ea3ef42560ce58e /target-arm | |
parent | 235ea1f5c89abf30e452539b973b0dbe43d3fe2b (diff) | |
download | qemu-50866ba5a2cfe922aaf3edb79f6eac5b0653477a.zip qemu-50866ba5a2cfe922aaf3edb79f6eac5b0653477a.tar.gz qemu-50866ba5a2cfe922aaf3edb79f6eac5b0653477a.tar.bz2 |
target-arm: Add write_type argument to cpsr_write()
Add an argument to cpsr_write() to indicate what kind of CPSR
write is being requested, since the exact behaviour should
differ for the different cases.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1455556977-3644-3-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm')
-rw-r--r-- | target-arm/cpu.h | 13 | ||||
-rw-r--r-- | target-arm/gdbstub.c | 2 | ||||
-rw-r--r-- | target-arm/helper.c | 3 | ||||
-rw-r--r-- | target-arm/kvm32.c | 2 | ||||
-rw-r--r-- | target-arm/kvm64.c | 2 | ||||
-rw-r--r-- | target-arm/machine.c | 2 | ||||
-rw-r--r-- | target-arm/op_helper.c | 6 |
7 files changed, 20 insertions, 10 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 3cbda73..87720d4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -718,8 +718,17 @@ static inline void pstate_write(CPUARMState *env, uint32_t val) /* Return the current CPSR value. */ uint32_t cpsr_read(CPUARMState *env); -/* Set the CPSR. Note that some bits of mask must be all-set or all-clear. */ -void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask); + +typedef enum CPSRWriteType { + CPSRWriteByInstr = 0, /* from guest MSR or CPS */ + CPSRWriteExceptionReturn = 1, /* from guest exception return insn */ + CPSRWriteRaw = 2, /* trust values, do not switch reg banks */ + CPSRWriteByGDBStub = 3, /* from the GDB stub */ +} CPSRWriteType; + +/* Set the CPSR. Note that some bits of mask must be all-set or all-clear.*/ +void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, + CPSRWriteType write_type); /* Return the current xPSR value. */ static inline uint32_t xpsr_read(CPUARMState *env) diff --git a/target-arm/gdbstub.c b/target-arm/gdbstub.c index 08b91a4..3ba9aad 100644 --- a/target-arm/gdbstub.c +++ b/target-arm/gdbstub.c @@ -94,7 +94,7 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) return 4; case 25: /* CPSR */ - cpsr_write(env, tmp, 0xffffffff); + cpsr_write(env, tmp, 0xffffffff, CPSRWriteByGDBStub); return 4; } /* Unknown register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 5a0447b..014bb80 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5233,7 +5233,8 @@ uint32_t cpsr_read(CPUARMState *env) | (env->GE << 16) | (env->daif & CPSR_AIF); } -void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) +void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, + CPSRWriteType write_type) { uint32_t changed_daif; diff --git a/target-arm/kvm32.c b/target-arm/kvm32.c index ea01932..d44a7f9 100644 --- a/target-arm/kvm32.c +++ b/target-arm/kvm32.c @@ -428,7 +428,7 @@ int kvm_arch_get_registers(CPUState *cs) if (ret) { return ret; } - cpsr_write(env, cpsr, 0xffffffff); + cpsr_write(env, cpsr, 0xffffffff, CPSRWriteRaw); /* Make sure the current mode regs are properly set */ mode = env->uncached_cpsr & CPSR_M; diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c index 0f1b4d6..08c2c81 100644 --- a/target-arm/kvm64.c +++ b/target-arm/kvm64.c @@ -723,7 +723,7 @@ int kvm_arch_get_registers(CPUState *cs) pstate_write(env, val); } else { env->uncached_cpsr = val & CPSR_M; - cpsr_write(env, val, 0xffffffff); + cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); } /* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the diff --git a/target-arm/machine.c b/target-arm/machine.c index ed1925a..0fc7df0 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -175,7 +175,7 @@ static int get_cpsr(QEMUFile *f, void *opaque, size_t size) /* Avoid mode switch when restoring CPSR */ env->uncached_cpsr = val & CPSR_M; - cpsr_write(env, val, 0xffffffff); + cpsr_write(env, val, 0xffffffff, CPSRWriteRaw); return 0; } diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index e3ddd5a..543d33a 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -422,13 +422,13 @@ uint32_t HELPER(cpsr_read)(CPUARMState *env) void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask) { - cpsr_write(env, val, mask); + cpsr_write(env, val, mask, CPSRWriteByInstr); } /* Write the CPSR for a 32-bit exception return */ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) { - cpsr_write(env, val, CPSR_ERET_MASK); + cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn); } /* Access to user mode registers from privileged modes. */ @@ -780,7 +780,7 @@ void HELPER(exception_return)(CPUARMState *env) if (!return_to_aa64) { env->aarch64 = 0; env->uncached_cpsr = spsr & CPSR_M; - cpsr_write(env, spsr, ~0); + cpsr_write(env, spsr, ~0, CPSRWriteRaw); if (!arm_singlestep_active(env)) { env->uncached_cpsr &= ~PSTATE_SS; } |