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| author | Alex Bennée <alex.bennee@linaro.org> | 2014-03-17 16:31:47 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-03-17 16:31:47 +0000 |
| commit | f612537e0706761d5692deaa72516695ef0a2ac8 (patch) | |
| tree | b705a57b3c3ec649395337b2dd5e37e4593cd251 /target-arm/translate-a64.c | |
| parent | 10113b6903c0256c1741918430b0304c5a60b7a8 (diff) | |
| download | qemu-f612537e0706761d5692deaa72516695ef0a2ac8.zip qemu-f612537e0706761d5692deaa72516695ef0a2ac8.tar.gz qemu-f612537e0706761d5692deaa72516695ef0a2ac8.tar.bz2 | |
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-5-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target-arm/translate-a64.c')
| -rw-r--r-- | target-arm/translate-a64.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 550decc..427f484 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6623,6 +6623,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, case 0x6f: /* FNEG */ gen_helper_vfp_negd(tcg_rd, tcg_rn); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env); + break; default: g_assert_not_reached(); } @@ -8392,6 +8395,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd); return; + case 0x7f: /* FSQRT */ + if (size == 3 && !is_q) { + unallocated_encoding(s); + return; + } + break; case 0x16: /* FCVTN, FCVTN2 */ case 0x17: /* FCVTL, FCVTL2 */ case 0x18: /* FRINTN */ @@ -8416,7 +8425,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x7b: /* FCVTZU */ case 0x7c: /* URSQRTE */ case 0x7d: /* FRSQRTE */ - case 0x7f: /* FSQRT */ unsupported_encoding(s, insn); return; default: @@ -8493,6 +8501,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ gen_helper_vfp_negs(tcg_res, tcg_op); break; + case 0x7f: /* FSQRT */ + gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); + break; default: g_assert_not_reached(); } |