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author | Greg Bellows <greg.bellows@linaro.org> | 2015-02-13 05:46:08 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2015-02-13 05:46:08 +0000 |
commit | ce02049dbf1828b4bc77d921b108a9d84246e5aa (patch) | |
tree | bc66b68d60c6999ffe2f327aa30bd97ab46512c7 /target-arm/helper-a64.c | |
parent | f313369fdb78f849ecbbd8e5d88f01ddf38786c8 (diff) | |
download | qemu-ce02049dbf1828b4bc77d921b108a9d84246e5aa.zip qemu-ce02049dbf1828b4bc77d921b108a9d84246e5aa.tar.gz qemu-ce02049dbf1828b4bc77d921b108a9d84246e5aa.tar.bz2 |
target-arm: Add 32/64-bit register sync
Add AArch32 to AArch64 register sychronization functions.
Replace manual register synchronization with new functions in
aarch64_cpu_do_interrupt() and HELPER(exception_return)().
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1423736974-14254-4-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target-arm/helper-a64.c')
-rw-r--r-- | target-arm/helper-a64.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 8aa40e9..7e0d038 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -466,7 +466,6 @@ void aarch64_cpu_do_interrupt(CPUState *cs) unsigned int new_el = arm_excp_target_el(cs, cs->exception_index); target_ulong addr = env->cp15.vbar_el[new_el]; unsigned int new_mode = aarch64_pstate_mode(new_el, true); - int i; if (arm_current_el(env) < new_el) { if (env->aarch64) { @@ -530,9 +529,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } env->elr_el[new_el] = env->regs[15]; - for (i = 0; i < 15; i++) { - env->xregs[i] = env->regs[i]; - } + aarch64_sync_32_to_64(env); env->condexec_bits = 0; } |