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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-04-15 19:18:41 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:04 +0100 |
| commit | aca3f40b374428e9c01068cf96294483cbb760a0 (patch) | |
| tree | ea0528c089b29a84a44cac1cd539d80917e51308 /target-arm/cpu64.c | |
| parent | 9225d739e7f6ec8d2139f79c3d2e3282cc725364 (diff) | |
| download | qemu-aca3f40b374428e9c01068cf96294483cbb760a0.zip qemu-aca3f40b374428e9c01068cf96294483cbb760a0.tar.gz qemu-aca3f40b374428e9c01068cf96294483cbb760a0.tar.bz2 | |
target-arm: A64: Implement DC ZVA
Implement the DC ZVA instruction, which clears a block of memory.
The fast path obtains a pointer to the underlying RAM via the TCG TLB
data structure so we can do a direct memset(), with fallback to a
simple byte-store loop in the slow path.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu64.c')
| -rw-r--r-- | target-arm/cpu64.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 8426bf1..fccecc2 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -46,6 +46,7 @@ static void aarch64_any_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_V7MP); set_feature(&cpu->env, ARM_FEATURE_AARCH64); cpu->ctr = 0x80030003; /* 32 byte I and D cacheline size, VIPT icache */ + cpu->dcz_blocksize = 7; /* 512 bytes */ } #endif |