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| author | Anthony Liguori <aliguori@amazon.com> | 2013-12-19 11:56:33 -0800 |
|---|---|---|
| committer | Anthony Liguori <aliguori@amazon.com> | 2013-12-19 11:56:33 -0800 |
| commit | 3dc7e2a3fedafc2f951bd62300b342c84e3606f8 (patch) | |
| tree | 21542d98c6aba2e48b12ee5db6fb0420a9f71ac8 /target-arm/cpu64.c | |
| parent | f46e720a82ccdf1a521cf459448f3f96ed895d43 (diff) | |
| parent | 84291fe7a34f8c2d595bcdb77ff506d1d60fcd7c (diff) | |
| download | qemu-3dc7e2a3fedafc2f951bd62300b342c84e3606f8.zip qemu-3dc7e2a3fedafc2f951bd62300b342c84e3606f8.tar.gz qemu-3dc7e2a3fedafc2f951bd62300b342c84e3606f8.tar.bz2 | |
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into staging
target-arm queue:
* AES instruction support for 32 bit ARM
* pflash01: much better emulation of 2x16bit and similar configs
where multiple flash devices are banked together
* fixed CBAR handling on Zynq, Highbank
* initial AArch64 KVM control support
* first two chunks of patches for A64 instruction emulation
* new board: canon-a1100 (Canon DIGIC SoC)
* new board: cubieboard (Allwinner A10 SoC)
# gpg: Signature made Tue 17 Dec 2013 12:18:39 PM PST using RSA key ID 14360CDE
# gpg: Can't check signature: public key not found
# By Alexander Graf (14) and others
# Via Peter Maydell
* pmaydell/tags/pull-target-arm-20131217: (62 commits)
MAINTAINERS: add myself to maintain allwinner-a10
hw/arm: add cubieboard support
hw/arm: add allwinner a10 SoC support
hw/intc: add allwinner A10 interrupt controller
hw/timer: add allwinner a10 timer
vmstate: Add support for an array of ptimer_state *
MAINTAINERS: Document 'Canon DIGIC' machine
hw/arm/digic: add NOR ROM support
hw/arm/digic: add UART support
hw/arm/digic: add timer support
hw/arm/digic: prepare DIGIC-based boards support
hw/arm: add very initial support for Canon DIGIC SoC
target-arm: A64: add support for logical (immediate) insns
target-arm: A64: add support for 1-src CLS insn
host-utils: add clrsb32/64 - count leading redundant sign bits
target-arm: A64: add support for bitfield insns
target-arm: A64: add support for 1-src REV insns
target-arm: A64: add support for 1-src RBIT insn
target-arm: A64: add support for 1-src data processing and CLZ
target-arm: A64: add support for 2-src shift reg insns
...
Message-id: 1387312160-12318-1-git-send-email-peter.maydell@linaro.org
Signed-off-by: Anthony Liguori <aliguori@amazon.com>
Diffstat (limited to 'target-arm/cpu64.c')
| -rw-r--r-- | target-arm/cpu64.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index 3e99c21..04ce879 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -68,11 +68,22 @@ static void aarch64_cpu_finalizefn(Object *obj) { } +static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) +{ + ARMCPU *cpu = ARM_CPU(cs); + /* + * TODO: this will need updating for system emulation, + * when the core may be in AArch32 mode. + */ + cpu->env.pc = value; +} + static void aarch64_cpu_class_init(ObjectClass *oc, void *data) { CPUClass *cc = CPU_CLASS(oc); cc->dump_state = aarch64_cpu_dump_state; + cc->set_pc = aarch64_cpu_set_pc; cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; cc->gdb_num_core_regs = 34; |