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| author | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 11:57:23 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-06-20 12:13:28 +0000 |
| commit | b2d06f9607e36333686b0e52a188881ce38495c7 (patch) | |
| tree | e45f5ccab101209d4cdd8642296b1ce5ec982d7e /target-arm/cpu.h | |
| parent | 4a9a539ffb5226009a1bb4aa3a569fcd80cf1436 (diff) | |
| download | qemu-b2d06f9607e36333686b0e52a188881ce38495c7.zip qemu-b2d06f9607e36333686b0e52a188881ce38495c7.tar.gz qemu-b2d06f9607e36333686b0e52a188881ce38495c7.tar.bz2 | |
target-arm: Remove ARM_CPUID_* macros
All the uses of ARM_CPUID() to vary behaviour have now been
removed, so we can delete the ARM_CPUID_* macros now.
The one exception is the TI915T/925T, because of its odd behaviour
where the MIDR value can be changed at runtime.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Diffstat (limited to 'target-arm/cpu.h')
| -rw-r--r-- | target-arm/cpu.h | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 27e398b..33afa18 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -606,36 +606,9 @@ static inline bool cp_access_ok(CPUARMState *env, conventional cores (ie. Application or Realtime profile). */ #define IS_M(env) arm_feature(env, ARM_FEATURE_M) -#define ARM_CPUID(env) (env->cp15.c0_cpuid) -#define ARM_CPUID_ARM1026 0x4106a262 -#define ARM_CPUID_ARM926 0x41069265 -#define ARM_CPUID_ARM946 0x41059461 #define ARM_CPUID_TI915T 0x54029152 #define ARM_CPUID_TI925T 0x54029252 -#define ARM_CPUID_SA1100 0x4401A11B -#define ARM_CPUID_SA1110 0x6901B119 -#define ARM_CPUID_PXA250 0x69052100 -#define ARM_CPUID_PXA255 0x69052d00 -#define ARM_CPUID_PXA260 0x69052903 -#define ARM_CPUID_PXA261 0x69052d05 -#define ARM_CPUID_PXA262 0x69052d06 -#define ARM_CPUID_PXA270 0x69054110 -#define ARM_CPUID_PXA270_A0 0x69054110 -#define ARM_CPUID_PXA270_A1 0x69054111 -#define ARM_CPUID_PXA270_B0 0x69054112 -#define ARM_CPUID_PXA270_B1 0x69054113 -#define ARM_CPUID_PXA270_C0 0x69054114 -#define ARM_CPUID_PXA270_C5 0x69054117 -#define ARM_CPUID_ARM1136 0x4117b363 -#define ARM_CPUID_ARM1136_R2 0x4107b362 -#define ARM_CPUID_ARM1176 0x410fb767 -#define ARM_CPUID_ARM11MPCORE 0x410fb022 -#define ARM_CPUID_CORTEXA8 0x410fc080 -#define ARM_CPUID_CORTEXA9 0x410fc090 -#define ARM_CPUID_CORTEXA15 0x412fc0f1 -#define ARM_CPUID_CORTEXM3 0x410fc231 -#define ARM_CPUID_ANY 0xffffffff #if defined(CONFIG_USER_ONLY) #define TARGET_PAGE_BITS 12 |