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authorbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-06-24 12:09:48 +0000
committerbalrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162>2007-06-24 12:09:48 +0000
commit610c3c8afd99f4f118b12ede39ee8d62ee44a446 (patch)
tree8ed525ee83d9096cdc40587e7042046b86b2f81d /target-arm/cpu.h
parentb6d7c3db4fd7b375e649b35c2d0722ef00f8fb35 (diff)
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Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3013 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'target-arm/cpu.h')
-rw-r--r--target-arm/cpu.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 80727bb..1c748e2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -83,6 +83,7 @@ typedef struct CPUARMState {
uint32_t c0_cachetype;
uint32_t c1_sys; /* System control register. */
uint32_t c1_coproc; /* Coprocessor access register. */
+ uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */
uint32_t c2_base; /* MMU translation table base. */
uint32_t c2_data; /* MPU data cachable bits. */
uint32_t c2_insn; /* MPU instruction cachable bits. */