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| author | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:01 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-02-26 17:20:01 +0000 |
| commit | 7da845b0f42a791d65045284f90977d636c654cc (patch) | |
| tree | 763ae33ac3ff89bff142de56afd8aeaaaf910480 /target-arm/cpu.c | |
| parent | 67ed771dedd2a7c6f094e0d70fb1fde8f5fb79da (diff) | |
| download | qemu-7da845b0f42a791d65045284f90977d636c654cc.zip qemu-7da845b0f42a791d65045284f90977d636c654cc.tar.gz qemu-7da845b0f42a791d65045284f90977d636c654cc.tar.bz2 | |
target-arm: A64: Make cache ID registers visible to AArch64
Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions.
CTR needs to have a split definition, but we can clean up the
temporary user-mode implementation in favour of using the CPU-specified
reset value, and implement the system-mode-required semantics of
restricting its EL0 accessibility if SCTLR.UCT is not set.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index fe18b65..8fed098 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -91,6 +91,8 @@ static void arm_cpu_reset(CPUState *s) env->aarch64 = 1; #if defined(CONFIG_USER_ONLY) env->pstate = PSTATE_MODE_EL0t; + /* Userspace expects access to CTL_EL0 */ + env->cp15.c1_sys |= SCTLR_UCT; #else env->pstate = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F | PSTATE_MODE_EL1h; |