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| author | Rob Herring <rob.herring@linaro.org> | 2014-04-15 19:18:42 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-04-17 21:34:04 +0100 |
| commit | 6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03 (patch) | |
| tree | 7b46494b34d745af65a5463a419a92a6e1bc011d /target-arm/cpu.c | |
| parent | 7e09797c299712cafa7bc05dd57c1b13afcc6039 (diff) | |
| download | qemu-6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03.zip qemu-6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03.tar.gz qemu-6cd8a2649aafb8e53db4a8f0bf0ea629441f8c03.tar.bz2 | |
target-arm: Implement AArch64 views of fault status and data registers
Implement AArch64 views of ESR_EL1 and FAR_EL1, and make the 32 bit
DFSR, DFAR, IFAR share state with them as architecturally specified.
The IFSR doesn't share state with any AArch64 register visible at EL1,
so just rename the state field without widening it to 64 bits.
Signed-off-by: Rob Herring <rob.herring@linaro.org>
[PMM: Minor tweaks; fix some bugs involving inconsistencies between
use of offsetof() or offsetoflow32() and struct field width]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Diffstat (limited to 'target-arm/cpu.c')
| -rw-r--r-- | target-arm/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index d62b792..a3c7492 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -425,7 +425,7 @@ static void arm1026_initfn(Object *obj) ARMCPRegInfo ifar = { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.c6_insn), + .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1), .resetvalue = 0 }; define_one_arm_cp_reg(cpu, &ifar); |