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| author | Max Filippov <jcmvbkbc@gmail.com> | 2023-11-30 09:19:19 -0800 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2024-01-19 12:28:59 +0100 |
| commit | 5f3ebbc86da5508535c7d8e4655b1dc7ad3047fe (patch) | |
| tree | a42d7521d364d327d759c2dda593bb5fe354e30a /system/arch_init.c | |
| parent | 396f66f99dfb405bd2a29582d043d2a6b7b37d6d (diff) | |
| download | qemu-5f3ebbc86da5508535c7d8e4655b1dc7ad3047fe.zip qemu-5f3ebbc86da5508535c7d8e4655b1dc7ad3047fe.tar.gz qemu-5f3ebbc86da5508535c7d8e4655b1dc7ad3047fe.tar.bz2 | |
target/xtensa: use generic instruction breakpoint infrastructure
Don't embed ibreak exception generation into TB and don't invalidate TB
on ibreak address change. Add CPUBreakpoint pointers to xtensa
CPUArchState, use cpu_breakpoint_insert/cpu_breakpoint_remove_by_ref to
manage ibreak breakpoints and provide TCGCPUOps::debug_check_breakpoint
callback that recognizes valid instruction breakpoints.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20231130171920.3798954-2-jcmvbkbc@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'system/arch_init.c')
0 files changed, 0 insertions, 0 deletions