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author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-05-18 16:03:09 +0200 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-05-21 22:05:27 +0100 |
commit | a50fe66846d1d02065265f1e54c2b0007f8cb609 (patch) | |
tree | 1e25486165f305f3873f4d7d8d2736d84d0942fd /stubs | |
parent | 492edf3e3038760aa6b7eb6a9bfdb648d4fa9b80 (diff) | |
download | qemu-a50fe66846d1d02065265f1e54c2b0007f8cb609.zip qemu-a50fe66846d1d02065265f1e54c2b0007f8cb609.tar.gz qemu-a50fe66846d1d02065265f1e54c2b0007f8cb609.tar.bz2 |
hw/timer/exynos4210_mct: Replace hw_error() by qemu_log_mask()
hw_error() calls exit(). This a bit overkill when we can log
the accesses as unimplemented or guest error.
When fuzzing the devices, we don't want the whole process to
exit. Replace some hw_error() calls by qemu_log_mask().
Per the datasheet "Exynos 4412 RISC Microprocessor Rev 1.00"
Chapter 25 "Multi Core Timer (MCT)" figure 1 and table 4,
the default value on the APB bus is 0.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200518140309.5220-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'stubs')
0 files changed, 0 insertions, 0 deletions