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author | Nicholas Piggin <npiggin@gmail.com> | 2021-05-01 17:24:35 +1000 |
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committer | David Gibson <david@gibson.dropbear.id.au> | 2021-05-04 13:12:46 +1000 |
commit | 526cdce771fa27c37b68fd235ff9f1caa0bdd563 (patch) | |
tree | 17ecd66691cbeb0e317e767001362a637200a3d0 /stubs | |
parent | 8b7e6b07a46809a75b857d30ae47e697e0f9b724 (diff) | |
download | qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.zip qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.tar.gz qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.tar.bz2 |
target/ppc: Add POWER10 exception model
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-3-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'stubs')
0 files changed, 0 insertions, 0 deletions