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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-19 13:51:07 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
| commit | f18708a53adc0549526fbeba5d1e892c0c4bf49c (patch) | |
| tree | 196a116b86aa8e3bd32640936a7f2a80526deb86 /stubs/cpu-synchronize-state.c | |
| parent | 67bedef51aa1144975c619f8559848819cdc309a (diff) | |
| download | qemu-f18708a53adc0549526fbeba5d1e892c0c4bf49c.zip qemu-f18708a53adc0549526fbeba5d1e892c0c4bf49c.tar.gz qemu-f18708a53adc0549526fbeba5d1e892c0c4bf49c.tar.bz2 | |
target/mips: Convert MSA 3R instruction format to decodetree (part 2/4)
Convert 3-register operations to decodetree.
Per the Encoding of Operation Field for 3R Instruction Format'
(Table 3.25), these instructions are not defined for the BYTE
format. Therefore the TRANS_DF_iii_b() macro returns 'false'
in that case, because no such instruction is decoded.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211028210843.2120802-22-f4bug@amsat.org>
Diffstat (limited to 'stubs/cpu-synchronize-state.c')
0 files changed, 0 insertions, 0 deletions