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| author | Peter Maydell <peter.maydell@linaro.org> | 2015-10-30 16:30:25 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-10-30 16:30:25 +0000 |
| commit | e79ea9e4240971b43494184d68a7f5a67d07e74b (patch) | |
| tree | 61cb35e3af977e54626c32038895d0f02e520cad /spice-qemu-char.c | |
| parent | fdf927621a99711bf1a81712bce054794f2d44c3 (diff) | |
| parent | 60270f85cc93d2d34e45b7679c374b1d771f0eeb (diff) | |
| download | qemu-e79ea9e4240971b43494184d68a7f5a67d07e74b.zip qemu-e79ea9e4240971b43494184d68a7f5a67d07e74b.tar.gz qemu-e79ea9e4240971b43494184d68a7f5a67d07e74b.tar.bz2 | |
Merge remote-tracking branch 'remotes/lalrae/tags/mips-20151030' into staging
MIPS patches 2015-10-30
Changes:
* R6 CPU can be woken up by non-enabled interrupts
* PC fix in KVM
* Coprocessor 0 XContext calculation fix
* various MIPS R6 updates
# gpg: Signature made Fri 30 Oct 2015 14:51:56 GMT using RSA key ID 0B29DA6B
# gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>"
* remotes/lalrae/tags/mips-20151030:
target-mips: fix updating XContext on mmu exception
target-mips: add SIGRIE instruction
target-mips: Set Config5.XNP for R6 cores
target-mips: add PC, XNP reg numbers to RDHWR
hw/mips_malta: Fix KVM PC initialisation
target-mips: Add enum for BREAK32
target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6
target-mips: implement the CPU wake-up on non-enabled interrupts in R6
target-mips: move the test for enabled interrupts to a separate function
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'spice-qemu-char.c')
0 files changed, 0 insertions, 0 deletions