aboutsummaryrefslogtreecommitdiff
path: root/semihosting
diff options
context:
space:
mode:
authorRichard Henderson <richard.henderson@linaro.org>2022-06-07 10:31:22 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-06-28 04:35:07 +0530
commit1b3b7693b7c3f94bd66a8425201a4bb7de5388e4 (patch)
treef3ff4105441e6ad13ff63acaef8605991e7b6759 /semihosting
parenta1df4bab432fc62a0d14abc192ce063c432afd2e (diff)
downloadqemu-1b3b7693b7c3f94bd66a8425201a4bb7de5388e4.zip
qemu-1b3b7693b7c3f94bd66a8425201a4bb7de5388e4.tar.gz
qemu-1b3b7693b7c3f94bd66a8425201a4bb7de5388e4.tar.bz2
semihosting: Split out common-semi-target.h
Move the ARM and RISCV specific helpers into their own header file. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Luc Michel <lmichel@kalray.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'semihosting')
-rw-r--r--semihosting/arm-compat-semi.c94
1 files changed, 1 insertions, 93 deletions
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 50f40a2..5e442e5 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -46,9 +46,6 @@
#else
#include "qemu/cutils.h"
#include "hw/loader.h"
-#ifdef TARGET_ARM
-#include "hw/arm/boot.h"
-#endif
#include "hw/boards.h"
#endif
@@ -182,96 +179,7 @@ static LayoutInfo common_semi_find_bases(CPUState *cs)
#endif
-#ifdef TARGET_ARM
-static inline target_ulong
-common_semi_arg(CPUState *cs, int argno)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- if (is_a64(env)) {
- return env->xregs[argno];
- } else {
- return env->regs[argno];
- }
-}
-
-static inline void
-common_semi_set_ret(CPUState *cs, target_ulong ret)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- if (is_a64(env)) {
- env->xregs[0] = ret;
- } else {
- env->regs[0] = ret;
- }
-}
-
-static inline bool
-common_semi_sys_exit_extended(CPUState *cs, int nr)
-{
- return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
-}
-
-static inline bool is_64bit_semihosting(CPUArchState *env)
-{
- return is_a64(env);
-}
-
-static inline target_ulong common_semi_stack_bottom(CPUState *cs)
-{
- ARMCPU *cpu = ARM_CPU(cs);
- CPUARMState *env = &cpu->env;
- return is_a64(env) ? env->xregs[31] : env->regs[13];
-}
-
-static inline bool common_semi_has_synccache(CPUArchState *env)
-{
- /* Ok for A64, invalid for A32/T32. */
- return is_a64(env);
-}
-#endif /* TARGET_ARM */
-
-#ifdef TARGET_RISCV
-static inline target_ulong
-common_semi_arg(CPUState *cs, int argno)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- return env->gpr[xA0 + argno];
-}
-
-static inline void
-common_semi_set_ret(CPUState *cs, target_ulong ret)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- env->gpr[xA0] = ret;
-}
-
-static inline bool
-common_semi_sys_exit_extended(CPUState *cs, int nr)
-{
- return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
-}
-
-static inline bool is_64bit_semihosting(CPUArchState *env)
-{
- return riscv_cpu_mxl(env) != MXL_RV32;
-}
-
-static inline target_ulong common_semi_stack_bottom(CPUState *cs)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- return env->gpr[xSP];
-}
-
-static inline bool common_semi_has_synccache(CPUArchState *env)
-{
- return true;
-}
-#endif
+#include "common-semi-target.h"
/*
* The semihosting API has no concept of its errno being thread-safe,