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| author | Richard Henderson <richard.henderson@linaro.org> | 2021-10-19 20:16:58 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair@alistair23.me> | 2021-10-22 07:47:51 +1000 |
| commit | db23e5d981ab22da0bfe1150f4828d08484b1fba (patch) | |
| tree | 14f4f3929206ac712fbdd06c0ab06b264e6b6d39 /semihosting/arm-compat-semi.c | |
| parent | e91a7227cb802ea62ffa14707ebc2f588b01213d (diff) | |
| download | qemu-db23e5d981ab22da0bfe1150f4828d08484b1fba.zip qemu-db23e5d981ab22da0bfe1150f4828d08484b1fba.tar.gz qemu-db23e5d981ab22da0bfe1150f4828d08484b1fba.tar.bz2 | |
target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl
Shortly, the set of supported XL will not be just 32 and 64,
and representing that properly using the enumeration will be
imperative.
Two places, booting and gdb, intentionally use misa_mxl_max
to emphasize the use of the reset value of misa.mxl, and not
the current cpu state.
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20211020031709.359469-5-richard.henderson@linaro.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'semihosting/arm-compat-semi.c')
| -rw-r--r-- | semihosting/arm-compat-semi.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 01badea..37963be 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -775,7 +775,7 @@ static inline bool is_64bit_semihosting(CPUArchState *env) #if defined(TARGET_ARM) return is_a64(env); #elif defined(TARGET_RISCV) - return !riscv_cpu_is_32bit(env); + return riscv_cpu_mxl(env) != MXL_RV32; #else #error un-handled architecture #endif |