diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2023-12-15 18:58:49 +1000 |
|---|---|---|
| committer | Nicholas Piggin <npiggin@gmail.com> | 2024-02-23 23:16:34 +1000 |
| commit | c8fd9667e5975fe2e70a906e125a758737eab707 (patch) | |
| tree | dd15ebe3037bf8131905433b2465a20d8b969a1f /scripts | |
| parent | 2cc0e449d17310877fb28a942d4627ad22bb68ea (diff) | |
| download | qemu-c8fd9667e5975fe2e70a906e125a758737eab707.zip qemu-c8fd9667e5975fe2e70a906e125a758737eab707.tar.gz qemu-c8fd9667e5975fe2e70a906e125a758737eab707.tar.bz2 | |
target/ppc: Fix crash on machine check caused by ifetch
is_prefix_insn_excp() loads the first word of the instruction address
which caused an exception, to determine whether or not it was prefixed
so the prefix bit can be set in [H]SRR1.
This works if the instruction image can be loaded, but if the exception
was caused by an ifetch, this load could fail and cause a recursive
exception and crash. Machine checks caused by ifetch are not excluded
from the prefix check and can crash (see issue 2108 for an example).
Fix this by excluding machine checks caused by ifetch from the prefix
check.
Cc: qemu-stable@nongnu.org
Acked-by: Cédric Le Goater <clg@kaod.org>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2108
Fixes: 55a7fa34f89 ("target/ppc: Machine check on invalid real address access on POWER9/10")
Fixes: 5a5d3b23cb2 ("target/ppc: Add SRR1 prefix indication to interrupt handlers")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions