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| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | 2023-10-16 12:17:33 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:02:17 +1000 |
| commit | b901c7eb701a8f4d512be3a70958150fc5d0cd90 (patch) | |
| tree | 040dfb7bc4b3550e11629407fbee606c1a20ce4d /scripts | |
| parent | d17bcae5f7e9f949052a1f126a7f23e7279b6d96 (diff) | |
| download | qemu-b901c7eb701a8f4d512be3a70958150fc5d0cd90.zip qemu-b901c7eb701a8f4d512be3a70958150fc5d0cd90.tar.gz qemu-b901c7eb701a8f4d512be3a70958150fc5d0cd90.tar.bz2 | |
target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled
With H-Ext supported, VS bits are all hardwired to one in MIDELEG
denoting always delegated interrupts. This is being done in rmw_mideleg
but given mideleg is used in other places when routing interrupts
this change initializes it in riscv_cpu_realize to be on the safe side.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-4-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions