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| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-10-09 18:05:51 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-10-18 20:37:20 +0200 |
| commit | 5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6 (patch) | |
| tree | aec770ca83d1d53eccd57353bf6b5e5eadea272a /scripts | |
| parent | 49735f76db25bf10f57973d5249f17151b801760 (diff) | |
| download | qemu-5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6.zip qemu-5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6.tar.gz qemu-5e31fdd59fda5c4ba9eb0daadc2a26273a29a0b6.tar.bz2 | |
target/mips: Add CP0 PWBase register
Add PWBase register (CP0 Register 5, Select 5).
The PWBase register contains the Page Table Base virtual address.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions