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authorDeepak Gupta <debug@rivosinc.com>2023-01-27 11:17:58 -0800
committerAlistair Francis <alistair.francis@wdc.com>2023-02-07 08:19:23 +1000
commit506c6698fbe53e88fba3160fc3842e5d41a9ee25 (patch)
treed8fb92cf852f20a971a9e7b6c522012517aa03f5 /scripts
parent179d9e2911f26088360a1d663767cf6612f96f44 (diff)
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target/riscv: fix for virtual instr exception
commit fb3f3730e4 added mechanism to generate virtual instruction exception during instruction decode when virt is enabled. However in some situations, illegal instruction exception can be raised due to state of CPU. One such situation is implementing branch tracking. [1] An indirect branch if doesn't land on a landing pad instruction, then cpu must raise an illegal instruction exception. Implementation would raise such expcetion due to missing landing pad inst and not due to decode. Thus DisasContext must have `virt_inst_excp` initialized to false during DisasContxt initialization for TB. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta <debug@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230127191758.755844-1-debug@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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