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| author | Anup Patel <anup.patel@wdc.com> | 2022-02-04 23:16:42 +0530 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-02-16 12:24:18 +1000 |
| commit | 32b0ada038629311aa90499a68de29473df7935d (patch) | |
| tree | 6c0e8aecc592dcbf74cc40c9b128dc3385d46ca0 /scripts | |
| parent | f87adf23fa66fd07d9f003173d386c0a54d9ddb0 (diff) | |
| download | qemu-32b0ada038629311aa90499a68de29473df7935d.zip qemu-32b0ada038629311aa90499a68de29473df7935d.tar.gz qemu-32b0ada038629311aa90499a68de29473df7935d.tar.bz2 | |
target/riscv: Add AIA cpu feature
We define a CPU feature for AIA CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating AIA CSRs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-id: 20220204174700.534953-7-anup@brainfault.org
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions