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| author | Richard Henderson <richard.henderson@linaro.org> | 2024-06-05 10:24:03 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2024-06-05 10:24:03 -0700 |
| commit | 535ad16c5d668f6185be2f88c6c82bf8e452c45d (patch) | |
| tree | 6d95d2e96f454a9d6cae021b0aa10f6e44d2e373 /scripts/shaderinclude.py | |
| parent | f1572ab94738bd5787b7badcd4bd93a3657f0680 (diff) | |
| parent | b12b72274320ce3ee516d963efd48766163cb240 (diff) | |
| download | qemu-535ad16c5d668f6185be2f88c6c82bf8e452c45d.zip qemu-535ad16c5d668f6185be2f88c6c82bf8e452c45d.tar.gz qemu-535ad16c5d668f6185be2f88c6c82bf8e452c45d.tar.bz2 | |
Merge tag 'pull-sp-20240605' of https://gitlab.com/rth7680/qemu into staging
target/sparc: Implement FMAF, IMA, VIS3 and VIS4 extensions
linux-user: Add ioctl for BLKBSZSET
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* tag 'pull-sp-20240605' of https://gitlab.com/rth7680/qemu: (38 commits)
target/sparc: Enable VIS4 feature bit
target/sparc: Implement monitor ASIs
target/sparc: Implement MWAIT
target/sparc: Implement SUBXC, SUBXCcc
target/sparc: Implement FPMIN, FPMAX
target/sparc: Implement VIS4 comparisons
target/sparc: Implement 8-bit FPADD, FPADDS, and FPADDUS
target/sparc: Implement FALIGNDATAi
target/sparc: Add feature bit for VIS4
target/sparc: Implement IMA extension
target/sparc: Enable VIS3 feature bit
target/sparc: Implement XMULX
target/sparc: Implement UMULXHI
target/sparc: Implement PDISTN
target/sparc: Implement MOVsTOw, MOVdTOx, MOVwTOs, MOVxTOd
target/sparc: Implement LZCNT
target/sparc: Implement LDXEFSR
target/sparc: Implement FSLL, FSRL, FSRA, FSLAS
target/sparc: Implement FPCMPEQ8, FPCMPNE8, FPCMPULE8, FPCMPUGT8
target/sparc: Implement FPADDS, FPSUBS
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'scripts/shaderinclude.py')
0 files changed, 0 insertions, 0 deletions