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| author | Glenn Miles <milesg@linux.ibm.com> | 2025-09-25 15:17:43 -0500 |
|---|---|---|
| committer | Harsh Prateek Bora <harshpb@linux.ibm.com> | 2025-09-28 23:26:52 +0530 |
| commit | 880aa4cb06ff5e86b6feab3030e14a16fea1dced (patch) | |
| tree | 8ae6c9149a16368f5818c99f23cdba0932a65426 /scripts/qapi/expr.py | |
| parent | 7928680e0aaf0c755ce97800791bf73185749a88 (diff) | |
| download | qemu-880aa4cb06ff5e86b6feab3030e14a16fea1dced.zip qemu-880aa4cb06ff5e86b6feab3030e14a16fea1dced.tar.gz qemu-880aa4cb06ff5e86b6feab3030e14a16fea1dced.tar.bz2 | |
target/ppc: Support for IBM PPE42 MMU
The IBM PPE42 processor only supports real mode
addressing and does not distinguish between
problem and supervisor states. It also uses
the IR and DR MSR bits for other purposes.
Therefore, add a check for PPE42 when we update
hflags and cause it to ignore the IR and DR bits
when calculating MMU indexes.
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20250925201758.652077-6-milesg@linux.ibm.com
Message-ID: <20250925201758.652077-6-milesg@linux.ibm.com>
Diffstat (limited to 'scripts/qapi/expr.py')
0 files changed, 0 insertions, 0 deletions