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| author | Glenn Miles <milesg@linux.ibm.com> | 2025-09-25 15:17:40 -0500 |
|---|---|---|
| committer | Harsh Prateek Bora <harshpb@linux.ibm.com> | 2025-09-28 23:26:51 +0530 |
| commit | 0af45e550b50f1c41164e5c0440654319942707e (patch) | |
| tree | 16e6af8f0d6635b7930066151a15d09597cafb6c /scripts/qapi/expr.py | |
| parent | 556d19fdcb1a07afc05bde7b38cfd2a1f4a89552 (diff) | |
| download | qemu-0af45e550b50f1c41164e5c0440654319942707e.zip qemu-0af45e550b50f1c41164e5c0440654319942707e.tar.gz qemu-0af45e550b50f1c41164e5c0440654319942707e.tar.bz2 | |
target/ppc: Add IBM PPE42 family of processors
Adds the IBM PPE42 family of 32-bit processors supporting
the PPE42, PPE42X and PPE42XM processor versions. These
processors are used as embedded processors in the IBM
Power9, Power10 and Power12 processors for various
tasks. It is basically a stripped down version of the
IBM PowerPC 405 processor, with some added instructions
for handling 64-bit loads and stores.
For more information on the PPE 42 processor please visit:
https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf
Supports PPE42 SPR's (Including the MSR).
Does not yet support exceptions, new PPE42 instructions and
does not prevent access to some invalid instructions and
registers (currently allows access to invalid GPR's and CR
fields).
Signed-off-by: Glenn Miles <milesg@linux.ibm.com>
Reviewed-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Link: https://lore.kernel.org/r/20250925201758.652077-3-milesg@linux.ibm.com
Message-ID: <20250925201758.652077-3-milesg@linux.ibm.com>
Diffstat (limited to 'scripts/qapi/expr.py')
0 files changed, 0 insertions, 0 deletions