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| author | Peter Maydell <peter.maydell@linaro.org> | 2021-07-23 17:21:44 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-07-27 10:57:39 +0100 |
| commit | 41487794f5af977e992870e18521bed88daa68d5 (patch) | |
| tree | 97425fa3b533a9ebe5b202d5d319d04ad218372d /scripts/oss-fuzz | |
| parent | d4f6883912dba8a710274e2364c440c210e4ec65 (diff) | |
| download | qemu-41487794f5af977e992870e18521bed88daa68d5.zip qemu-41487794f5af977e992870e18521bed88daa68d5.tar.gz qemu-41487794f5af977e992870e18521bed88daa68d5.tar.bz2 | |
hw/intc/armv7m_nvic: ISCR.ISRPENDING is set for non-enabled pending interrupts
The ISCR.ISRPENDING bit is set when an external interrupt is pending.
This is true whether that external interrupt is enabled or not.
This means that we can't use 's->vectpending == 0' as a shortcut to
"ISRPENDING is zero", because s->vectpending indicates only the
highest priority pending enabled interrupt.
Remove the incorrect optimization so that if there is no pending
enabled interrupt we fall through to scanning through the whole
interrupt array.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-5-peter.maydell@linaro.org
Diffstat (limited to 'scripts/oss-fuzz')
0 files changed, 0 insertions, 0 deletions