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| author | Tomasz Jeznach <tjeznach@rivosinc.com> | 2024-10-16 17:40:29 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-31 13:51:24 +1000 |
| commit | b9b283260e810afc7e0117e41827070f315c3f96 (patch) | |
| tree | f8fe42200751054872dd15169602df98e3fcb312 /scripts/nsis.py | |
| parent | 3c445dacc47f43d2e66280d393b71ac8e5bb01bb (diff) | |
| download | qemu-b9b283260e810afc7e0117e41827070f315c3f96.zip qemu-b9b283260e810afc7e0117e41827070f315c3f96.tar.gz qemu-b9b283260e810afc7e0117e41827070f315c3f96.tar.bz2 | |
hw/riscv: add riscv-iommu-pci reference device
The RISC-V IOMMU can be modelled as a PCIe device following the
guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU
as a PCIe device".
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241016204038.649340-6-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/nsis.py')
0 files changed, 0 insertions, 0 deletions