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| author | Tomasz Jeznach <tjeznach@rivosinc.com> | 2024-10-16 17:40:34 -0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-31 13:51:24 +1000 |
| commit | a7aa525b93c3f7a847cd2185b71aef97a17ec3d5 (patch) | |
| tree | 87626293935fac26df9bc33be73c5414f9641c4e /scripts/nsis.py | |
| parent | 69a9ae483696e185889edaeddacf46afd9110bc6 (diff) | |
| download | qemu-a7aa525b93c3f7a847cd2185b71aef97a17ec3d5.zip qemu-a7aa525b93c3f7a847cd2185b71aef97a17ec3d5.tar.gz qemu-a7aa525b93c3f7a847cd2185b71aef97a17ec3d5.tar.bz2 | |
hw/riscv/riscv-iommu: add DBG support
DBG support adds three additional registers: tr_req_iova, tr_req_ctl and
tr_response.
The DBG cap is always enabled. No on/off toggle is provided for it.
Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241016204038.649340-11-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/nsis.py')
0 files changed, 0 insertions, 0 deletions