aboutsummaryrefslogtreecommitdiff
path: root/scripts/nsis.py
diff options
context:
space:
mode:
authorChao Gao <chao.gao@intel.com>2024-09-19 13:10:11 +0800
committerPaolo Bonzini <pbonzini@redhat.com>2024-10-17 12:30:21 +0200
commit10eaf9c0fb7060f45807becbb2742a9de9bc3632 (patch)
tree6fe202593911a3dde66f32e6de6a4613666e4dec /scripts/nsis.py
parent87c88db3143e91076d167a62dd7febf49afca8a2 (diff)
downloadqemu-10eaf9c0fb7060f45807becbb2742a9de9bc3632.zip
qemu-10eaf9c0fb7060f45807becbb2742a9de9bc3632.tar.gz
qemu-10eaf9c0fb7060f45807becbb2742a9de9bc3632.tar.bz2
target/i386: Add more features enumerated by CPUID.7.2.EDX
Following 5 bits in CPUID.7.2.EDX are supported by KVM. Add their supports in QEMU. Each of them indicates certain bits of IA32_SPEC_CTRL are supported. Those bits can control CPU speculation behavior which can be used to defend against side-channel attacks. bit0: intel-psfd if 1, indicates bit 7 of the IA32_SPEC_CTRL MSR is supported. Bit 7 of this MSR disables Fast Store Forwarding Predictor without disabling Speculative Store Bypass bit1: ipred-ctrl If 1, indicates bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported. Bit 3 of this MSR enables IPRED_DIS control for CPL3. Bit 4 of this MSR enables IPRED_DIS control for CPL0/1/2 bit2: rrsba-ctrl If 1, indicates bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported. Bit 5 of this MSR disables RRSBA behavior for CPL3. Bit 6 of this MSR disables RRSBA behavior for CPL0/1/2 bit3: ddpd-u If 1, indicates bit 8 of the IA32_SPEC_CTRL MSR is supported. Bit 8 of this MSR disables Data Dependent Prefetcher. bit4: bhi-ctrl if 1, indicates bit 10 of the IA32_SPEC_CTRL MSR is supported. Bit 10 of this MSR enables BHI_DIS_S behavior. Signed-off-by: Chao Gao <chao.gao@intel.com> Link: https://lore.kernel.org/r/20240919051011.118309-1-chao.gao@intel.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'scripts/nsis.py')
0 files changed, 0 insertions, 0 deletions