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| author | Rajnesh Kanwal <rkanwal@rivosinc.com> | 2023-10-16 12:17:34 +0100 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-11-07 11:02:17 +1000 |
| commit | 1ebad505f3d5108513bf150b901344caceb3a7c1 (patch) | |
| tree | 48647564dccaa213aaf964daf90e069d285de4c6 /scripts/coverage | |
| parent | b901c7eb701a8f4d512be3a70958150fc5d0cd90 (diff) | |
| download | qemu-1ebad505f3d5108513bf150b901344caceb3a7c1.zip qemu-1ebad505f3d5108513bf150b901344caceb3a7c1.tar.gz qemu-1ebad505f3d5108513bf150b901344caceb3a7c1.tar.bz2 | |
target/riscv: Split interrupt logic from riscv_cpu_update_mip.
This is to allow virtual interrupts to be inserted into S and VS
modes. Given virtual interrupts will be maintained in separate
mvip and hvip CSRs, riscv_cpu_update_mip will no longer be in the
path and interrupts need to be triggered for these cases from
rmw_hvip64 and rmw_mvip64 functions.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-5-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'scripts/coverage')
0 files changed, 0 insertions, 0 deletions