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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-08-13 12:36:46 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-08-25 13:02:14 +0200 |
| commit | 71ed30b7d4c7bc7d8069eba601d7384e378f3024 (patch) | |
| tree | 9865c4c2e45c54286a3e87dfbc34535a104e8cf7 /scripts/analyse-9p-simpletrace.py | |
| parent | 98d207cf9c232e6ac451b2aba24baa007956f578 (diff) | |
| download | qemu-71ed30b7d4c7bc7d8069eba601d7384e378f3024.zip qemu-71ed30b7d4c7bc7d8069eba601d7384e378f3024.tar.gz qemu-71ed30b7d4c7bc7d8069eba601d7384e378f3024.tar.bz2 | |
target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr
Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter
1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements
48 virtual address bits in each 64-bit segment, not 40.
Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Message-Id: <20210813110149.1432692-3-f4bug@amsat.org>
Diffstat (limited to 'scripts/analyse-9p-simpletrace.py')
0 files changed, 0 insertions, 0 deletions