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| author | Zhenzhong Duan <zhenzhong.duan@intel.com> | 2024-12-12 16:37:45 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-01-15 13:06:15 -0500 |
| commit | fed51ee5e02d8779ccbdce555e556c4ada321281 (patch) | |
| tree | 25f3da4e444dfd6832e186e24d4f4c27e013d9a1 /rust/qemu-api | |
| parent | 305e469b7188e5f1a896c40853d84fa158ee6ba4 (diff) | |
| download | qemu-fed51ee5e02d8779ccbdce555e556c4ada321281.zip qemu-fed51ee5e02d8779ccbdce555e556c4ada321281.tar.gz qemu-fed51ee5e02d8779ccbdce555e556c4ada321281.tar.bz2 | |
intel_iommu: Check stage-1 translation result with interrupt range
Per VT-d spec 4.1 section 3.15, "Untranslated requests and translation
requests that result in an address in the interrupt range will be
blocked with condition code LGN.4 or SGN.8."
This applies to both stage-1 and stage-2 IOMMU page table, move the
check from vtd_iova_to_slpte() to vtd_do_iommu_translate() so stage-1
page table could also be checked.
By this chance, update the comment with correct section number.
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-9-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'rust/qemu-api')
0 files changed, 0 insertions, 0 deletions