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| author | Zhenzhong Duan <zhenzhong.duan@intel.com> | 2024-12-12 16:37:41 +0800 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-01-15 13:06:07 -0500 |
| commit | ad0a7f1e1edbe841d4285a6b56f071eb3de9c86c (patch) | |
| tree | a26638fb1157206fd043b19ce7aaaa5c58cdc7b7 /rust/qemu-api | |
| parent | 791346f93d2aa3b7eaebf4a12f4b7c558e94ff6b (diff) | |
| download | qemu-ad0a7f1e1edbe841d4285a6b56f071eb3de9c86c.zip qemu-ad0a7f1e1edbe841d4285a6b56f071eb3de9c86c.tar.gz qemu-ad0a7f1e1edbe841d4285a6b56f071eb3de9c86c.tar.bz2 | |
intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb invalidation
Per VT-d spec 4.1, 6.5.2.4, "Table 21. PASID-based-IOTLB Invalidation",
PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb
entries with matching domain id and pasid.
With stage-1 translation introduced, guest could send PASID-selective
PASID-based iotlb invalidation to flush either stage-1 or stage-2 entries.
By this chance, remove old IOTLB related definitions which were unused.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-5-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'rust/qemu-api')
0 files changed, 0 insertions, 0 deletions