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| author | Jamin Lin <jamin_lin@aspeedtech.com> | 2025-03-07 11:59:23 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-03-09 14:36:53 +0100 |
| commit | ab24c6a2df8e6c8055b6f1dfe80697320b327c50 (patch) | |
| tree | 0449c601e56a1b54eec227a5d91204fe3cb7276a /rust/qemu-api | |
| parent | c6c5e63d46add459732d8d8d3b84bd5d26dff0ad (diff) | |
| download | qemu-ab24c6a2df8e6c8055b6f1dfe80697320b327c50.zip qemu-ab24c6a2df8e6c8055b6f1dfe80697320b327c50.tar.gz qemu-ab24c6a2df8e6c8055b6f1dfe80697320b327c50.tar.bz2 | |
hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin numbers for input and output are different.
It is difficult to use a formula to determine the index number of INTC model
supported input and output IRQs.
To simplify and improve readability, introduces the AspeedINTCIRQ structure to
save the input/output IRQ index and its enable/status register address.
Introduce the "aspeed_2700_intc_irqs" table to store IRQ information for INTC.
Introduce the "aspeed_intc_get_irq" function to retrieve the input/output IRQ
pin index from the provided status/enable register address.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250307035945.3698802-15-jamin_lin@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'rust/qemu-api')
0 files changed, 0 insertions, 0 deletions