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author | Song Gao <gaosong@loongson.cn> | 2025-03-05 14:33:11 +0800 |
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committer | Song Gao <gaosong@loongson.cn> | 2025-03-07 10:15:08 +0800 |
commit | d882c284a3d4472d827e49a7357198b611900b08 (patch) | |
tree | 37cb8a90ba5f27b26a6cd2a02c28c3dba5d2bfd8 /rust/qemu-api/src/timer.rs | |
parent | 089fa3d7302b38285ae146de8bbe5cf6ecc04f34 (diff) | |
download | qemu-d882c284a3d4472d827e49a7357198b611900b08.zip qemu-d882c284a3d4472d827e49a7357198b611900b08.tar.gz qemu-d882c284a3d4472d827e49a7357198b611900b08.tar.bz2 |
target/loongarch: check tlb_ps
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps,
to make sure the tlb_ps is avalablie. we check tlb_ps
when get the tlb_ps from tlb->misc or CSR bits.
1. cpu reset
set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits a default value
from CSR_PRCFG2;
2. tlb instructions.
some tlb instructions get the tlb_ps from tlb->misc but the
value may has been initialized to 0. we need just check the tlb_ps
skip the function and write a guest log.
3. csrwr instructions.
to make sure CSR_PWCL.PTBASE and CSR_STLBPS.PS bits are avalable,
cheke theses bits and set a default value from CSR_PRCFG2.
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20250305063311.830674-3-gaosong@loongson.cn>
Diffstat (limited to 'rust/qemu-api/src/timer.rs')
0 files changed, 0 insertions, 0 deletions