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| author | BALATON Zoltan <balaton@eik.bme.hu> | 2025-02-10 17:03:29 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-03-11 20:00:16 +0100 |
| commit | d060b2789f71e8cd1d07c4374e0c96c299423952 (patch) | |
| tree | a98e43783a66793a367b0bfbde7519fc35f3c939 /rust/qemu-api/src/module.rs | |
| parent | 825b96dbcee23d134b691fc75618b59c5f53da32 (diff) | |
| download | qemu-d060b2789f71e8cd1d07c4374e0c96c299423952.zip qemu-d060b2789f71e8cd1d07c4374e0c96c299423952.tar.gz qemu-d060b2789f71e8cd1d07c4374e0c96c299423952.tar.bz2 | |
hw/sd/sdhci: Set reset value of interrupt registers
The interrupt enable registers are not reset to 0 on Freescale eSDHC
but some bits are enabled on reset. At least some U-Boot versions seem
to expect this and not initialise these registers before expecting
interrupts. Use existing vendor property for Freescale eSDHC and set
the reset value of the interrupt registers to match Freescale
documentation.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20250210160329.DDA7F4E600E@zero.eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Diffstat (limited to 'rust/qemu-api/src/module.rs')
0 files changed, 0 insertions, 0 deletions