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| author | Yao Xingtao <yaoxt.fnst@fujitsu.com> | 2025-02-03 16:19:08 +0000 |
|---|---|---|
| committer | Michael S. Tsirkin <mst@redhat.com> | 2025-02-21 07:18:42 -0500 |
| commit | 9ac2c42f43a536f53b3d4cad8a601ccb8640cbd8 (patch) | |
| tree | 2ca5c8009f64c6e7c250edfd70bc85b2f768015f /rust/qemu-api/src/memory.rs | |
| parent | d3c92cf6dcab028d05f306d4d50511aa805d2385 (diff) | |
| download | qemu-9ac2c42f43a536f53b3d4cad8a601ccb8640cbd8.zip qemu-9ac2c42f43a536f53b3d4cad8a601ccb8640cbd8.tar.gz qemu-9ac2c42f43a536f53b3d4cad8a601ccb8640cbd8.tar.bz2 | |
mem/cxl_type3: support 3, 6, 12 and 16 interleave ways
Since the kernel does not check the interleave capability, a
3-way, 6-way, 12-way or 16-way region can be create normally.
Applications can access the memory of 16-way region normally because
qemu can convert hpa to dpa correctly for the power of 2 interleave
ways, after kernel implementing the check, this kind of region will
not be created any more.
For non power of 2 interleave ways, applications could not access the
memory normally and may occur some unexpected behaviors, such as
segmentation fault.
So implements this feature is needed.
Link: https://lore.kernel.org/linux-cxl/3e84b919-7631-d1db-3e1d-33000f3f3868@fujitsu.com/
Signed-off-by: Yao Xingtao <yaoxt.fnst@fujitsu.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20250203161908.145406-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Diffstat (limited to 'rust/qemu-api/src/memory.rs')
0 files changed, 0 insertions, 0 deletions