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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-02-12 16:43:30 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-20 14:20:29 +0000 |
| commit | 92fea7f2e7818d3019b5c29eb8379049a3b1f0c4 (patch) | |
| tree | 2c36b67030c6a431d6c5baf18b8d265cee70fc8e /rust/qemu-api/src/memory.rs | |
| parent | 2d269a8bbb7fc7148f429b13720c7b5d07bba3c0 (diff) | |
| download | qemu-92fea7f2e7818d3019b5c29eb8379049a3b1f0c4.zip qemu-92fea7f2e7818d3019b5c29eb8379049a3b1f0c4.tar.gz qemu-92fea7f2e7818d3019b5c29eb8379049a3b1f0c4.tar.bz2 | |
hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs
Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
on Appendix A: Register Details, the mpcore Interrupt Controller Type
Register (ICDICTR) has the IT_Lines_Number field read-only with value
0x2, described as:
IT_Lines_Number
b00010 = the distributor provides 96 interrupts,
64 external interrupt lines.
Add a GIC_EXT_IRQS definition (with a comment) to make the number of
GIC external IRQs explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'rust/qemu-api/src/memory.rs')
0 files changed, 0 insertions, 0 deletions