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authorPeter Maydell <peter.maydell@linaro.org>2025-01-30 18:23:05 +0000
committerPeter Maydell <peter.maydell@linaro.org>2025-02-20 14:20:28 +0000
commit2d60f1acdb950e85335b018bcaf4ba0f042a350c (patch)
treeebf2fd0eeb8dc5ab64be616448bc9ec225b86df2 /rust/qemu-api/src/memory.rs
parent273d0e84ccd1f0a94f893d2f1ab750f812dfa219 (diff)
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target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1
We currently use CP_ACCESS_TRAP in a number of access functions where we know we're currently at EL0; in this case the "usual target EL" is EL1, so CP_ACCESS_TRAP and CP_ACCESS_TRAP_EL1 behave the same. Use CP_ACCESS_TRAP_EL1 to more closely match the pseudocode for this sort of check. Note that in the case of the access functions foc cacheop to PoC or PoU, the code was correct but the comment was wrong: SCTLR_EL1.UCI traps for DC CVAC, DC CIVAC, DC CVAP, DC CVADP, DC CVAU and IC IVAU should be system access traps, not UNDEFs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250130182309.717346-11-peter.maydell@linaro.org
Diffstat (limited to 'rust/qemu-api/src/memory.rs')
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