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| author | Philippe Mathieu-Daudé <philmd@linaro.org> | 2025-02-12 16:43:27 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-02-20 14:20:29 +0000 |
| commit | 284e354566c31687cce260401549a616cf513c60 (patch) | |
| tree | 5f0c82e2c9132470b2d9014a184056fb04d2726b /rust/qemu-api/src/memory.rs | |
| parent | 4ac4d6e77613ccbb9aa55675429dc0b9ae1f8ea6 (diff) | |
| download | qemu-284e354566c31687cce260401549a616cf513c60.zip qemu-284e354566c31687cce260401549a616cf513c60.tar.gz qemu-284e354566c31687cce260401549a616cf513c60.tar.bz2 | |
hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250212154333.28644-3-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'rust/qemu-api/src/memory.rs')
0 files changed, 0 insertions, 0 deletions