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| author | Steven Lee <steven_lee@aspeedtech.com> | 2025-05-02 18:34:40 +0800 |
|---|---|---|
| committer | Cédric Le Goater <clg@redhat.com> | 2025-05-05 09:38:55 +0200 |
| commit | c528f10dce8eeaabe97f216d6488a6b8509b7067 (patch) | |
| tree | cf90a6b8df6b8a83eea731707ad412c5eeda4125 /rust/qemu-api-macros | |
| parent | 8872b6717c37001e8f2e6c4ed0af20b1811d8f58 (diff) | |
| download | qemu-c528f10dce8eeaabe97f216d6488a6b8509b7067.zip qemu-c528f10dce8eeaabe97f216d6488a6b8509b7067.tar.gz qemu-c528f10dce8eeaabe97f216d6488a6b8509b7067.tar.bz2 | |
hw/intc/aspeed: Add support for AST2700 TSP INTC
- Define new types for ast2700tsp INTC and INTCIO
- Add register definitions for TSP INTC and INTCIO
- Implement write handlers for TSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the TSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:
- AST2700
Support GICINT128 to GICINT136 in INTC
The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-tsp
Support TSPINT128 to TSPINT136 in INTC
The INTCIO TSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> TSPINT 160
Bit 1 -> TSPINT 161
Bit 2 -> TSPINT 162
Bit 3 -> TSPINT 163
Bit 4 -> TSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: I3f3aca4b90129640369cf4a92deb4b9a12df5b70
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-5-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'rust/qemu-api-macros')
0 files changed, 0 insertions, 0 deletions