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| author | Deepak Gupta <debug@rivosinc.com> | 2024-10-08 15:49:52 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2024-10-30 11:22:08 +1000 |
| commit | bd08b22e5648d90ed256a505da75809d0ab6be00 (patch) | |
| tree | 23fc6b642f573d1d5994217bfda294d33c10be33 /rust/qemu-api-macros/src | |
| parent | f9158a92404b9aec29f36ad1139b92f493d56604 (diff) | |
| download | qemu-bd08b22e5648d90ed256a505da75809d0ab6be00.zip qemu-bd08b22e5648d90ed256a505da75809d0ab6be00.tar.gz qemu-bd08b22e5648d90ed256a505da75809d0ab6be00.tar.bz2 | |
target/riscv: Add zicfilp extension
zicfilp [1] riscv cpu extension enables forward control flow integrity.
If enabled, all indirect calls must land on a landing pad instruction.
This patch sets up space for zicfilp extension in cpuconfig. zicfilp
is dependend on zicsr.
[1] - https://github.com/riscv/riscv-cfi
Signed-off-by: Deepak Gupta <debug@rivosinc.com>
Co-developed-by: Jim Shu <jim.shu@sifive.com>
Co-developed-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20241008225010.1861630-3-debug@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'rust/qemu-api-macros/src')
0 files changed, 0 insertions, 0 deletions