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author | Steven Lee <steven_lee@aspeedtech.com> | 2025-05-02 18:34:39 +0800 |
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committer | Cédric Le Goater <clg@redhat.com> | 2025-05-05 09:38:55 +0200 |
commit | 8872b6717c37001e8f2e6c4ed0af20b1811d8f58 (patch) | |
tree | 660261cc3ad7fc088ead96dd548c65fbd8350070 /rust/qemu-api-macros/src | |
parent | 78110f821aa0c372bb8141ce8ec9f543f8660c36 (diff) | |
download | qemu-8872b6717c37001e8f2e6c4ed0af20b1811d8f58.zip qemu-8872b6717c37001e8f2e6c4ed0af20b1811d8f58.tar.gz qemu-8872b6717c37001e8f2e6c4ed0af20b1811d8f58.tar.bz2 |
hw/intc/aspeed: Add support for AST2700 SSP INTC
- Define new types for ast2700ssp INTC and INTCIO
- Add register definitions for SSP INTC and INTCIO
- Implement write handlers for SSP INTC and INTCIO
- Register new types in aspeed_intc_register_types
The design of the SSP INTC and INTCIO controllers is similar to
AST2700, with the following differences:
- AST2700
Support GICINT128 to GICINT136 in INTC
The INTCIO GIC_192_201 has 10 output pins, mapped as follows:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
- AST2700-ssp
Support SSPINT128 to SSPINT136 in INTC
The INTCIO SSPINT_160_169 has 10 output pins, mapped as follows:
Bit 0 -> SSPINT 160
Bit 1 -> SSPINT 161
Bit 2 -> SSPINT 162
Bit 3 -> SSPINT 163
Bit 4 -> SSPINT 164
Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>
Change-Id: Ib8cb0e264505cef48e17f173e057f3b2d1ea35c4
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250502103449.3091642-4-steven_lee@aspeedtech.com
Signed-off-by: Cédric Le Goater <clg@redhat.com>
Diffstat (limited to 'rust/qemu-api-macros/src')
0 files changed, 0 insertions, 0 deletions