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author | Paolo Bonzini <pbonzini@redhat.com> | 2022-10-19 13:22:06 +0200 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2022-10-20 15:16:18 +0200 |
commit | cf5ec6641ed456e2748b211b7bbf5103bfc93098 (patch) | |
tree | 84e5a3c059e7de484c1c7d66714c68e8d60ca9e1 /roms/seabios-hppa | |
parent | 314d3eff66f41f39191aaca2e5f6e3dc81480c1b (diff) | |
download | qemu-cf5ec6641ed456e2748b211b7bbf5103bfc93098.zip qemu-cf5ec6641ed456e2748b211b7bbf5103bfc93098.tar.gz qemu-cf5ec6641ed456e2748b211b7bbf5103bfc93098.tar.bz2 |
target/i386: implement F16C instructions
F16C only consists of two instructions, which are a bit peculiar
nevertheless.
First, they access only the low half of an YMM or XMM register for the
packed-half operand; the exact size still depends on the VEX.L flag.
This is similar to the existing avx_movx flag, but not exactly because
avx_movx is hardcoded to affect operand 2. To this end I added a "ph"
format name; it's possible to reuse this approach for the VPMOVSX and
VPMOVZX instructions, though that would also require adding two more
formats for the low-quarter and low-eighth of an operand.
Second, VCVTPS2PH is somewhat weird because it *stores* the result of
the instruction into memory rather than loading it.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'roms/seabios-hppa')
0 files changed, 0 insertions, 0 deletions