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| author | Shuuichirou Ishii <ishii.shuuichir@fujitsu.com> | 2021-08-31 17:29:38 +0900 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2021-09-01 11:08:18 +0100 |
| commit | e31c70ac04001df5e540b79843834277e283fa71 (patch) | |
| tree | 9ae5c7f2027ea30e953df4b390a429d9b8dbdcae /qobject | |
| parent | d4cc1c21965b3df527cbfbae5a317a9c2ac441e5 (diff) | |
| download | qemu-e31c70ac04001df5e540b79843834277e283fa71.zip qemu-e31c70ac04001df5e540b79843834277e283fa71.tar.gz qemu-e31c70ac04001df5e540b79843834277e283fa71.tar.bz2 | |
target-arm: Add support for Fujitsu A64FX
Add a definition for the Fujitsu A64FX processor.
The A64FX processor does not implement the AArch32 Execution state,
so there are no associated AArch32 Identification registers.
For SVE, the A64FX processor supports only 128,256 and 512bit vector
lengths.
The Identification register values are defined based on the FX700,
and have been tested and confirmed.
Signed-off-by: Shuuichirou Ishii <ishii.shuuichir@fujitsu.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'qobject')
0 files changed, 0 insertions, 0 deletions