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| author | Frank Chang <frank.chang@sifive.com> | 2022-04-20 16:08:58 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-04-22 10:35:16 +1000 |
| commit | d42df0ea5dd58cfda5e1466487f93b5b90a67594 (patch) | |
| tree | d3491de7164e8c661d83821f3665e484364d88c5 /qobject/json-lexer.c | |
| parent | 231a90c08545a7f903800d2ffb988dad08947460 (diff) | |
| download | qemu-d42df0ea5dd58cfda5e1466487f93b5b90a67594.zip qemu-d42df0ea5dd58cfda5e1466487f93b5b90a67594.tar.gz qemu-d42df0ea5dd58cfda5e1466487f93b5b90a67594.tar.bz2 | |
hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT
RISC-V privilege spec defines that:
* In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part
of the register.
* For RV64, naturally aligned 64-bit memory accesses to the mtime and
mtimecmp registers are additionally supported and are atomic.
It's possible to perform both 32/64-bit read/write accesses to both
mtimecmp and mtime registers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Message-Id: <20220420080901.14655-3-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'qobject/json-lexer.c')
0 files changed, 0 insertions, 0 deletions